Title: IP CORE DESIGN OF MICROCONTROLLER SYSTEM USING VERILOG FOR ROBOT BASED AGRICULTURAL IMPLEMENTS

Year of Publication: Jun - 2012
Page Numbers: 213-227
Authors: C. S. Mala, S. Ramachandran
Conference Name: The International Conference on Informatics and Applications (ICIA2012)
- Malaysia

Abstract:


This paper presents an RTL compliant Verilog IP Core design of a Microcontroller System modeled on the popular 8051 of Intel. This requirement primarily stems from the on-going project to design a Robot based Agricultural Implement. The proposed system consists of a core processor which emulates the existing 8051 Microcontroller. The designed core has 4K internal ROM, 128 bytes of internal RAM, address generator, decoder, external 64 KB RAM and external 60 KB ROM. The external RAM and ROM is user configurable. The IP Core realizes most of the 8051 features except that connected with serial communication. They have been fully tested using a comprehensive Test bench, also coded using Verilog. The RTL design is platform and technology independent. The Agricultural Implement design has been targeted on the Xilinx FPGA, Spartan 3, 200. The designed system is more efficient in terms of processing speed by over 8 to 50 times when compared to the original Intel‟s 8051.