Title: Wide Range Analog CMOS Multiplier for Neural Network Application
Issue Number: | Vol. 8, No. 2 |
Year of Publication: | Jun - 2018 |
Page Numbers: | 106-109 |
Authors: | Hassan Jouni, Adnan Harb, Gilles Jacquemod, Yves Leduc |
Journal Name: | International Journal of Digital Information and Wireless Communications (IJDIWC) - Hong Kong |
DOI: http://dx.doi.org/10.17781/P002415
Abstract:
This paper presents the design of a four quadrant analog CMOS multiplier for neural network applications. The input range is 100% of the power supply voltage. The circuit has been designed and tested in Cadence Virtuoso environment with the HCMOS9A (ST Microelectronics) 130-nm technology. In this type of multiplier, there are two voltage inputs and a single ended current output. The power supply is 0.9 V, and the power dissipation is approximately about 4 μW.