Title: VDA-Place: Voltage-Drop-Aware Standard Cell Placement

Year of Publication: Dec - 2014
Page Numbers: 200-205
Authors: Antonios N. Dadaliaris, George Dimitriou, Georgios I. Stamoulis
Conference Name: The International Conference on Computer Science, Computer Engineering, and Social Media (CSCESM2014)
- Greece

Abstract:


Voltage drop is becoming increasingly significant as integrated circuit (IC) fabrication processes move beyond 45nm, affecting both timing and reliability. We propose an IR-Drop based detailed standard cell placer that can achieve significant optimization of up to 6% for the timing of the critical path of a design. Our placer works incrementally to existing placers and is, thus, easier to integrate into existing industrial design flows.