Title: SER Analysis for Multiple Affected Gates

Year of Publication: Dec - 2014
Page Numbers: 193-199
Authors: Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, George Dimitriou, Georgios I. Stamoulis
Conference Name: The International Conference on Computer Science, Computer Engineering, and Social Media (CSCESM2014)
- Greece


Reliability of VLSI circuits had always been a major issue during the design process. It becomes more significant if we consider that modern integrated circuits are extremely sensitive to various factors such as noise and radiation. Therefore, it is crucial to implement tools for the evaluation of the vulnerability of the modern chips to the aforementioned hazards. In this paper, we present a Soft Error Rate estimation methodology for digital integrated circuits exposed to radiation effects, based on Monte-Carlo simulations. Unlike previous approaches, the particle hit affects more than one gate and, thus, more than one node of a circuit. The implemented tool incorporates all three masking effects - logical, electrical and timing - in order to determine, according to calculated latching probabilities, whether one or more of the SETs will be latched from flip-flops. Finally, SER of the circuit is estimated considering varying values of pulse width and scaling.