Title: Optimization of an Integrated Circuit Placement Algorithm in a Parallel Environment

Year of Publication: Dec - 2014
Page Numbers: 179-192
Authors: Stavros K. Ioannidis, Dimos Ntioudis, Charalampos Antoniadis, Antonios N. Dadaliaris, Panagiota Tsompanopoulou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
Conference Name: The International Conference on Computer Science, Computer Engineering, and Social Media (CSCESM2014)
- Greece


This paper presents an implementation of GORDIAN [1], a method for Global Placement of standard-cell based circuit designs, incorporating a number of algorithmic optimizations and parallelization in order to reduce the total runtime and memory requirements and improve the solution quality. Experimental results are presented, comparing GODRIAN to other state-of-the-art academic placers, which highlight the improved execution speed and the limited memory footprint which are GORDIAN’s main advantages. Thus, GORDIAN runs faster than any other proven placer while still producing acceptable results, enabling million-cell designs to be placed within a few minutes.