Title: Numerical Block High-Level Synthesis

Year of Publication: Dec - 2014
Page Numbers: 29-40
Authors: Michael Dossis, Vasilios Hados, Georgios Dimitriou
Conference Name: The International Conference on Computer Science, Computer Engineering, and Social Media (CSCESM2014)
- Greece


Nowadays, contemporary complex digital integrated circuits (ICs) are very difficult to deliver in the market on time. Therefore, formal, fully automated and rapid methods are needed for designing and developing complex ICs. In this work such formal methods exploit compiler technology, High-level Synthesis (HLS) and Electronic System Level (ESL) techniques that handle such complexity with success. Custom VLSI hardware units are cumbersome to develop and verify with traditional methods, and large arithmetic blocks such as floating-point and other numerical units are developed in this work, using our HLS tools. Here, the formal and fully automated CubedC HLS framework is used to rapidly deliver numerical hardware block implementations on FPGAs and ASICs. The provably-correct generated numerical modules include floating-point and trigonometric functions. Due to the formality of our techniques, time-consuming RTL and gate-level simulations are not needed. The numerical block specifications are modeled in ADA and/or ANSI-C high-level programming code, and competitive performance is achieved with our rapid CubedC experiments, making the presented approach highly useable.