Title: Hardware Architecture of FAST Algorithm for Feature Point Detection

Year of Publication: Feb - 2015
Page Numbers: 16-21
Authors: Chang-Sue Seo, Hoon-Ju Chung, Sung-Young Kim, Sangook Moon, Yong-Hwan Lee
Conference Name: The Second International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2015)
- Philippines


In this paper, we present method that detects useful feature points based on hardware architecture. We propose hardware architecture that uses the algorithm of FAST-n[1]. Feature point detection process needs extensive computing power and processing time. Therefore, we build hardware structure for real-time processing. The structure of the hardware is as follows. After loading the images in parallel, finding feature point candidates and selecting valid feature point modules operate simultaneously and independently using pipeline structure to reduce processing time. Proposed hardware architecture will operate in about 20,000 cycles in case of 320 x 240 resolution image. If our hardware structure is used for 1080p, the performance of processing will be about 70fps.