Title: Design, Implementation and Trial Evaluation of CPU Simulator to Visualize Register-transfer level Micro-Operation

Year of Publication: Jul - 2017
Page Numbers: 7-12
Authors: Shinya Hara, Yoshiro Imai, Koji Kagawa, Kazuaki Ando, Rihito Yaegashi, Keizo Saisho, Kyosuke Takahashi, Hitoshi Inomo, Naka Gotoda, Toshihiro Hayashi, Hiroyuki Tominaga, Tomohiko Takagi
Conference Name: The Third International Conference on Electronics and Software Science (ICESS2017)
- Japan


This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program code (instead of machine language), demonstration of several kinds of sample programs and visualization of register-transfer-level structure/behavior, namely micro-operation. Our educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU and understand micro-operation based behavior of CPU. Our Simulator has been also evaluated through some kinds of questionnaires by users/learners in classroom lectures. It is confirmed that the simulator has been very useful and effective to learn Computer Architecture and behav- ior/organization of CPU by means of its application.