Title: Compact Physical Model of TSV for Quick and Accurate Exploration of 3DICs

Year of Publication: Dec - 2014
Page Numbers: 165-172
Authors: Michalis Zervas, Maria Spanou, George Dimitriou, Georgios I. Stamoulis
Conference Name: The International Conference on Computer Science, Computer Engineering, and Social Media (CSCESM2014)
- Greece

Abstract:


This paper presents a novel physics-based analytical TSV model that allows fast and accurate design space exploration of signal propagation and attenuation properties in 3D ICs, and represents a useful tool for circuit designers and process engineers. A through silicon via(TSV), is a vertical interconnection method between chips and also is the critical enabling technology for three-dimensional integrated circuits (3D ICs). The model equations are based on simple process data including physical dimensions, passivation thickness, substrate doping, and TSV type without requiring full access to process parameters of a particular TSV technology. Working the other way around, by setting the parasitic threshold voltage and minimum MOS capacitance of a specific TSV, the model can provide a list of process specifications. The model has been validated against measured results published in literature. Our experiments show that TSV parasitic MOS capacitor threshold voltage and minimum capacitance values computed using the aforementioned model are within 25% and 5% of measured data. The resulting complex RLC model, taking into account the coupling effects between neighboring TSVs as well, has been experimentally validated under DC and high-frequency AC conditions. Moreover, timing libraries compatible with conventional EDA tools have been generated to run realistic timing analysis for 3D stacked integrated circuits, such as 3D I/Os.