Title: AN AREA REDUCTION TECHNIQUE FOR LOGIC SYNTHESIS OF NEURAL NETWORKS

Year of Publication: 2013
Page Numbers: 108-118
Authors: Noritaka Shigei, Masahiro Teramuray, Hiromi Miyajima, Naohiro Tateishi
Conference Name: The Second International Conference on Digital Enterprise and Information Systems (DEIS2013)
- Malaysia

Abstract:


This paper proposes a logic synthesis algorithm for neural networks (NNs). The logic circuit obtained by the proposed algorithm does not use multipliers and is rounding error free. Therefore, the proposed method is suitable for a low cost device with no hard macro of multiplier. The advantage over conventional methods is to reduce hardware resource usages without sacrificing output precision. The proposed algorithm sequentially converts each of multiple neural units constituting a given NN into a logic circuit, and in order to reduce the number of logic gates, it utilizes the input-output characteristics of neural units already converted. The proposed method is compared with a conventional method by using three types of benchmark NNs. The evaluation results on the number of logic gates show that, the reduction rate increases with the number of neural units and its maximum is 19.4%. Further, the results for implementation on CPLD (Complex Programmable Logic Device) show that the maximum reduction rate is 11.6%.