Title: A Survey: Load Balanced Routing Techniques in Network-on-Chips

Year of Publication: Nov - 2016
Page Numbers: 127-133
Authors: Ashwag Hamoud Alotebi, Soha Zaghloul Mekki
Conference Name: The Fifth International Conference on Informatics and Applications (ICIA2016)
- Japan


In all network types, load balancing is an essential issue that drastically affects the overall system performance. Interconnection networks are no exception. A Network-on-Chip (NoC) is one of the main components used to build an interconnection network. Its importance is due to it being used to simultaneously communicate between various system components and, therefore, introducing a highly efficient parallel system. In other words, a NoC offers a highly parallel scheme that interconnects between network interfaces, processors, memory modules, and routers in large-scale systems with no additional interaction from the designer. Therefore, NoCs provide enhanced reusability, scalability, and performance. Additionally, the implemented routing algorithm highly affects the performance of the NoC. A network load imbalance results in increasing packets latency, thereby decreasing the throughput. Thus, the overall system performance is negatively affected. This paper exposes some of the recently developed load balanced techniques specially designed for NoCs. The aim of this study is to investigate the main concept, the outcomes and the limitations of each routing algorithm. In addition, some recommended solutions to improve the NoC performance are suggested.